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دانلود اموزش رید گرفتن از گوشی های هواوی سری cpu mtk و غیره بدون باکس به وسیله sp flash tool با لینک مستقیم
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دانلود آموزش حل مشکل Encryption unsuccessful هارد هواوی با CPU MTKبعد از فرمت یا فلش با لینک مستقیم
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CPU cache
Diagram of a CPU memory cacheA CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations. As long as most memory accesses are to cached memory locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main memory.
The diagram to the right shows two memories. Each location in each memory has a datum (a cache line), which in different designs ranges in size from 8 to 512 bytes. The size of the cache line is usually larger than the size of the usual access requested by a CPU instruction, which ranges from 1 to 16 bytes. Each location in each memory also has an index, which is a unique number used to refer to that location. The index for a location in main memory is called an address. Each location in the cache has a tag, which contains the index of the datum in main memory which has been cached. In a CPU's data cache, these entries are called cache lines or cache blocks.
When the processor wishes to read or write a location in main memory, it first checks whether that memory location is in the cache. This is accomplished by comparing the address of the memory location to all tags in the cache that might contain that address. If the processor finds that the memory location is in the cache, we say that a cache hit has occurred, otherwise we speak of a cache miss. In the case of a cache hit, the processor immediately reads or writes the data in the cache line. The proportion of accesses that result in a cache hit is known as the hit rate, and is a measure of the effectiveness of the cache.
In the case of a cache miss, most caches allocate a new entry, which comprises the tag just missed and a copy of the data from memory. The reference can then be applied to the new entry just as in the case of a hit. Misses are comparatively slow because they require the data to be transferred from main memory. This transfer incurs a delay since main memory is much slower than cache memory, and also incurs the overhead for recording the new data in the cache before it is delivered to the processor.
Contents
1 Some details of operation
2 Associativity
3 Cache misses
4 Address translation
4.1 Virtual indexing and virtual aliases
4.2 Virtual tags and vhints
4.3 Page coloring
5 Cache hierarchy in a modern processor
5.1 Specialized caches
5.1.1 Victim cache
5.1.2 Trace cache
5.1.3 Harvard architecture
5.2 Multi-level caches
5.3 Example: the K8
5.4 More hierarchies
6 Implementation
7 See also
8 References
9 External links
Some details of operation
In order to make room for the new entry on a cache miss, the cache generally has to evict one of the existing entries. The heuristic that it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future is difficult, especially for hardware caches which use simple rules amenable to implementation in circuitry, so there are a variety of replacement policies to choose from and no perfect way to decide among them. One popular replacement policy, LRU, replaces the least recently used entry.
When data is written to the cache, it must at some point be written to main memory as well. The timing of this write is controlled by what is known as the write policy. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back or copy-back cache, writes are not immediately mirrored to memory. Instead, the cache tracks which locations have been written over (these locations are marked dirty). The data in these locations is written back to main memory when that data is evicted from the cache. For this reason, a miss in a write-back cache will often require two memory accesses to service: one to read the new location from memory and the other to write the dirty location to memory.
شامل 29 صفحه Wrod
CPU تراشه intel 925XE
18 صفحه
برای پشتیبانی از پردازنده با FSB جدید اینتل تراشه i925XE را بهینه ساخته است . i925XE بر پایه تراشه i925X که چهار ماه پیش از سوی اینتل معرفی شده بود طراحی شده است . تراشه جدید با i925X از نظر ظاهری هیچ تفاوتی نمیکند اما از نظر تکنولوژی پشتیبانی از FSB 1066MHz در آن تدبیر شده است . پشتیبانی از حافظه های ECC در این تراشه گنجانده نشده است با وجود اینکه i925X این امکان را دارا بود شکل زیر نمایی از دیاگرام مادربردی است که بر پایه i925XE طراحی شده است .
با وجود اینکه تا کنون فقط یک CPU با FSB 1066MHz از سوی اینتل معرفی شده است , انتظار میرود که پلتفورم های مبتنی بر تراشه i925XE آینده روشنی را پیش رو داشته باشند . این پلتفورم ها میزبان تمام پردازنده های Pentium 4 سری 600 و 700 (سریDual Core)خواهند بود .
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